TPS24711DGSR【PDF 20/34 页】IC CTRLR HOT SWAP 2.5-18V 10MSOP

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Sheet目录47

16页 17页 18页 19页 [20页]21页 22页 23页 24页

TPS24710,TPS24711

TPS24712,TPS24713

SLVSAL2E JANUARY 2011REVISED NOVEMBER 2013

www.ti.com

Figure 33. Latch After Overload Fault

PG, FLT, PGb, FLTb, AND TIMER OPERATIONS

The open-drain PG/PGb (PG is for TPS24712/13 and PGb is for TPS24710/11) output provides a deglitched

end-of-inrush indication based on the voltage across M

. PG/PGb is useful for preventing a downstream dc/dc

converter from starting while its input capacitor C

OUT

is still charging. PG goes active-high and PGb goes active-

low about 3.4 ms after C

OUT

is charged. This delay allows M

to fully turn on and any transients in the power

circuits to end before the converter starts up. This type of sequencing prevents the downstream converter from

demanding full current before the power-limiting engine allows the MOSFET to conduct the full current set by the

current limit I

LIM

. Failure to observe this precaution may prevent the system from starting. The pullup resistor

shown on the PG/PGb pin in the typical application diagram on the front page is illustrative only; the actual

connection to the converter depends on the application. The PG/PGb pin may indicate that inrush has ended

before the MOSFET is fully enhanced, but the downstream capacitor will have been charged to substantially its

full operating voltage. Care should be taken to ensure that the MOSFET on-resistance is sufficiently small to

ensure that the voltage drop across this transistor is less than the minimum power-good threshold of 140 mV.

After the hot-swap circuit successfully starts up, the PG pin can return to a low-impedance status and PGb to

high-impedance status whenever the drain-to-source voltage of MOSFET M

exceeds its upper threshold of

340 mV, which presents the downstream converters a warning flag. This flag may occur as a result of overload

fault, output short fault, input overvoltage, higher die temperature, or the GATE shutdown by UVLO and EN.

FLT/FLTb (FLT is for TPS24712/13 and FLTb is for TPS24710/11) is an indicator that the allowed fault-timer

period during which the load current can exceed the programmed current limit (but not the fast-trip threshold) has

expired. The fault timer starts when a current of approximately 10 糀 begins to flow into the external capacitor,

, and ends when the voltage of C

reaches TIMER upper threshold, i.e., 1.35 V. FLT goes high and FLTb pulls

low at the end of the fault timer. Otherwise, FLT assumes a low-impedance state and FLTb a high-impedance

state.

The fault-timer state requires an external capacitor C

connected between the TIMER pin and GND pin. The

length of the fault timer is the charging time of C

from 0 V to its upper threshold of 1.35 V. The fault timer begins

to count under any of the following three conditions:

1. In the inrush mode, TIMER begins to source current to the timer capacitor, C

, when MOSFET M

enabled. TIMER begins to sink current from the timer capacitor, C

when V

(GATE VCC)

exceeds the timer

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